The invention relates to a delay locked loop that synchronizes an output clock with an input clock by delaying the input clock via a controllable delay path. The controllable delay time is set by a feedback loop containing a phase detector and a filter. The invention additionally relates to a method for operating such a delay locked loop.
A delay locked loop (DLL) is used in integrated circuits in order to synchronize an on-chip clock signal with a clock signal fed in externally. In today""s electronic systems, for example in motherboards of personal computers, the various integrated circuits forming the system are operated clock-synchronously. Ever faster clock rates require that the specific timing specifications of the exchanged signals be complied with as exactly as possible. The available timing margins become smaller, so that the clock signals must be synchronized with one another as accurately as possible. A DLL has the task of carrying out this synchronization for a respective integrated circuit.
In particular, synchronously operating dynamic semiconductor memories, so-called SDRAMS (Synchronous Dynamic Random Access Memories) have a DLL which synchronizes an internal clock signal with a clock signal fed in from off-chip. The internally generated clock signal controls, for example, the time validation for the data signals that will be output. This compensates for the internal delay times of the fed-in clock signal on the semiconductor chip, so that the output data are present with a specific phase angle relative to the external operating clock. In the DLL, a phase detector determines the deviation between the external clock and the internal clock and accordingly readjusts the internal clock that is provided at the output of the DLL in a manner dependent on the external clock fed to the input of the DLL.
The filter, which sets the variable delay time of the delay path, ensures that the adjustment of the delay time by connecting in or disconnecting delay elements is not effective for every phase change that can occur in principle in every clock cycle. Previous filter concepts have the disadvantage that the delay time is adjusted only after the iteration of a fixed number of clock cycles. This number of clock cycles is independent of the phase difference between the input clock and the output clock. This means that the delay locked loop has different reaction times depending on the measure of the phase difference. The transient recovery time particularly in the case of a comparatively large phase difference that will be corrected is therefore relatively long.
U.S. Pat. No. 5,994,934 shows a delay locked loop having an external feedback loop and also an internal feedback loop that attaches to the loop filter and eliminates lock problems in the event of an excessive delay time (xe2x80x9cLock Deviation Phenomenonxe2x80x9d). The delay locked loop otherwise has a delay circuit with a controllable delay time, a phase detector and also the loop filter.
U.S. Pat. No. 6,157,690 shows a digital phase locked loop in which the delay path can be controlled by a control circuit in order to effect an immediate phase shift, in the event of a comparatively large phase error, and a less rapidly executed phase correction in the event of a comparatively small phase error.
Published Japanese Patent Application JP 58-161426 shows the embodiment of a loop filter with flip-flops, shift registers and logic combination elements for a digital phase locked loop.
It is accordingly an object of the invention to provide a delay locked loop and a method for operating the delay locked loop which overcomes the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide a delay locked loop whose transient recovery duration is always as short as possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, a delay locked loop, including: an input for obtaining a signal to be delayed; an output for providing a delayed signal; and a delay circuit connected between the input and the output. The delay circuit has an output and a controllable delay time. The delay locked loop also includes a phase detector having an input coupled to the input for obtaining the signal to be delayed. The phase detector has another input coupled to the output of the delay circuit. The phase detector has an output. The delay locked loop also includes a filter having: a first input being controlled by the output of the phase detector; an output coupled to the delay circuit to control the delay time of the delay circuit; a multistage counter having counter stages connected between the first input and the output, and a second input. The delay locked loop also includes a control logic circuit for feeding back the output of the filter to the second input of the filter in order to control a number of the counter stages that are effective between the first input of the filter and the output of the filter.
In accordance with an added feature of the invention, the first input of the filter includes at least two inputs; the output of the filter includes at least two outputs; the at least two inputs of the filter and the at least two outputs of the filter are connected between the phase detector and the delay circuit; one of the at least two outputs of the filter is provided for increasing the delay time of the delay circuit; another one of the at least two outputs of the filter is provided for reducing the delay time of the delay circuit; the counter stages of the multistage counter of the filter include a first counter connected between a respective one of the at least two inputs of the filter and a respective one of the at least two outputs of the filter; and the counter stages of the multistage counter of the filter include a second counter connected between a respective one of the at least two inputs of the filter and a respective one of the at least two outputs of the filter.
In accordance with an additional feature of the invention, the control logic circuit includes an output; the first counter and the second counter each include at least a first stage having an output, a second stage having an input, and a changeover switch connected between the first stage and the second stage; the changeover switch is controlled by the output of the control logic circuit; the changeover switch has a first switch position in which the output of the first stage is coupled with the input of the second stage; and the changeover switch has a second switch position in which the output of the first stage is coupled with one of the outputs of the filter.
In accordance with another feature of the invention, an integrator for accumulating a number of pulses at the output of the filter; a comparison logic device for comparing the number of the pulses being accumulated by the integrator with a first reference value; and the comparison logic device, in a manner dependent on the comparing, controlling the number of the counter stages that are effective.
In accordance with a further feature of the invention, the first reference value is formed in a manner dependent on the number of the counter stages that are effective.
In accordance with a further added feature of the invention, the comparison logic device includes a counter for counting a number of pulses of the signal to be delayed; the comparison logic device includes a first comparator for comparing the number of the pulses that have been counted with a further reference value; the comparison logic device includes a second comparator for, in a manner prompted by the first comparator, comparing the number of the pulses at the output of the filter with the first reference value; and the number of the pulses at the output of the filter is generated by the integrator.
In accordance with a further additional feature of the invention, the number of the counter stages that are effective is reduced if a number of pulses at the output of the filter exceeds a first reference value within a predetermined number of pulses of the signal to be delayed; and the number of the counter stages that are effective is increased if the number of the pulses at the output of the filter falls below the first reference value within the predetermined number of pulses of the signal to be delayed.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method for operating the delay locked loop. The method includes steps of: providing the delay locked loop; reducing the number of the counter stages that are effective if a number of pulses at the output of the filter exceeds a first reference value within a predetermined number of pulses of the signal to be delayed; and increasing the number of the counter stages that are effective if the number of the pulses at the output of the filter falls below the first reference value within the predetermined number of pulses of the signal to be delayed.
In other words, the method for operating such a delay locked loop includes the fact that the number of effective counter stages is reduced if the number of pulses at the output of the filter exceeds a first reference value within a predetermined number of pulses of the clock signal that can be fed in at the input of the delay locked loop, and that the number of effective counter stages of the counter of the filter is increased if the number of pulses at the output of the filter falls below the first reference value within the predetermined number of pulses of the clock signal that can be fed to the input of the delay locked loop.
In the case of the delay locked loop and the method, the filter has a counter that is controlled by a further, internal feedback loop which feeds the output of the counter back to a further input of the counter. The additional internal feedback loop controls the number of effective counter stages of the multistage counter. In the event of a large phase deviation between the input signal and the output signal of the delay locked loop, few counter stages will be activated, so that the transient recovery time is shortened. The delay time of the controllable delay path is adjusted depending on these pulses. The number of pulses is therefore a measure of the phase deviation between the output clock signal and the input clock signal of the delay locked loop. If the number of the output pulses of the delay locked loop exceeds a predetermined first reference value, this is interpreted to the effect that the phase difference is relatively large. The number of effective counter stages is therefore automatically reduced in order to accelerate the adjustment of the delay time of the delay path and thus the transient recovery process. Conversely, if the number of output pulses of the filter falls below this reference value, this means that the phase deviation is small. The number of effective counter stages is thereupon increased in order thereby to increase the stability of the control.
By virtue of the additional internal control loop, counter stages are automatically connected in or disconnected, so that ultimately, a predetermined reaction time of the delay locked loop is always ensured. The sensitivity of the delay locked loop is thus set adaptively to the measure of the phase difference between the internal clock signal to be generated and the clock signal that is fed in externally. The phasing of the delay locked loop to the clock fed in externally is thereby reduced.
As is known, the current consumption of a digital circuit realized in CMOS circuitry is determined by the switching frequency of the gates. Since electronic systems are in many cases embodied in a portable and battery-operated manner, endeavors are made to keep the current consumption as low as possible. The current consumption of a delay locked loop arranged on an SDRAM (Synchronous Dynamic Random Access Memory), for example, is not inconsiderable. Fast phasing means fewer changes in the time delay of the delay path and fewer switching operations. The current consumption of the SDRAM is therefore reduced by the circuit according to the invention.
A development of the invention provides for the filter to have a first output in order to reduce the delay time of the delay circuit. Each of the outputs is assigned a counter which, on the input side, is driven in turn by a separate output of the phase detector. The cascaded stages of the counter are connected in and disconnected in each case in parallel and in the same way.
A control logic device generates corresponding control signals in order to effect the connecting-in and disconnection of the individual counter stages. For this purpose, a changeover switch is arranged between two counter stages. This changeover switch has a first switch position that connects the output of an upstream-connected counter stage to the input of a downstream-connected counter stage. A second switch position of the changeover switch taps off the output of an upstream-connected counter stage and connects it directly to the corresponding output of the filter. The downstream counter stages are deactivated by this bypass.
The internal feedback loop attaches to the abovementioned output terminals of the filter and counts or accumulates the number of output pulses at the filter. For this purpose, a counting logic device which is referred to as an integrator is used and may be embodied as a binary or shift counter and can be reset in various ways. By way of example, the integrator can count only counting pulses of the same sense by being incremented only when successive pulses are output for increasing the delay time or reducing the delay time of the delay circuit. When the type of pulse changes, the integrator is reset and integrates from the beginning. On the other hand, the integrator can be embodied as an up and down counter, in which case it counts in one direction in the case of pulses of one type and in the other direction in the case of pulses of the other type.
The number of pulses counted by the integrator is compared with a first reference value. If the number of pulses is higher than the reference value then this means that there is a large phase shift to be corrected. On account of a pulse of the phase detector, an output pulse of the counter for adjusting the delay circuit is therefore to be generated with the shortest possible reaction time. Consequently, in this case, higher-value counter stages of the counter are disconnected or circumvented by the bypass. If the number of output pulses of the counter which is accumulated by the integrator lies below the reference value, this means that the input signals have only a small phase shift with respect to one another and the adjustment of the delay circuit should therefore be slowed down. Therefore, higher-value counter stages are supplementarily connected in an effective fashion.
The described comparison of the number of pulses counted by the integrator logic with the first reference value is expediently effected after a specific time window has elapsed. For this purpose, the number of the clock edges of the externally supplied clock signal is counted or accumulated and compared with a further reference value. The further reference value specifies the size of the time window. If the number of counted clock pulses reaches the further reference value, the comparison described above is performed.
For further adaptation of the control, the abovementioned first reference value, which enters into the comparison of the number of the output pulses of the filter that are counted by the integrator, is set adaptively in a manner dependent on the number of effective counter stages. By way of example, the first reference value is formed by specifying a desired value that is additionally divided by the number of effective counter stages in order to form the first reference value.
The method of operation described above and the circuit features described above are arranged in the additionally formed internal control loop, which feeds the output of the filter back to the further inputs of the filter. As described, this controls, in particular, the number of effective counter stages of the counter of the filter. The method of operation described is realized in the form of wired logic; that is to say with counters, registers and logic gates. Finally, the delay locked loop of the invention overall achieves a transient recovery duration that is as short as possible, an optimized current consumption and a reaction time that is as constant as possible. This is because the additional control loop adaptively takes account of the instantaneous operating conditions of the delay locked loop.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a delay locked loop, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.